Light-emitting device and the manufacturing method thereof

ABSTRACT

A light-emitting device, comprising: a substrate comprising an upper surface; an ion implantation region in the substrate; a semiconductor layer formed on the upper surface; a light-emitting stack formed on the semiconductor layer; and multiple cavities formed between the semiconductor layer and the upper surface in accordance with the ion implantation region.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Continuation-in-Part of co-pending applicationSer. No. 13/918,374, filed on Jun. 14, 2013, and for which priority isclaimed under 35 U.S.C. §120, the entire contents of all of which arehereby incorporated by reference.

TECHNICAL FIELD

The application relates to a light-emitting device, in particular,relates to a light-emitting device including scattering cavities thereinresulting from ion implantation.

DESCRIPTION OF BACKGROUND ART

The lighting theory and structure of light-emitting diode (LED) isdifferent from that of conventional lighting source. An LED hasadvantages as a low power loss, a long life-time, no need for warmingtime, and fast responsive time. Moreover, it is small, shockproof,suitable for mass production, so LEDs are widely adopted in the market.For example, LEDs can be used in optical display apparatus, laserdiodes, traffic lights, data storage devices, communication devices,illumination devices, medical devices, and so on.

A light-emitting device may include a substrate, a light-emitting stackincluding an n-type semiconductor layer, an active layer, and a p-typesemiconductor layer. The light-emitting stack may have roughenedstructure on the surface or the substrate thereof to enhance lightextraction.

In addition, the light emitting device can be further connected to othercomponents in order to form a light emitting apparatus. Thelight-emitting device may be mounted onto a submount with the side ofthe substrate, or a solder bump or a glue material may be formed betweenthe submount and the light-emitting device, therefore a light-emittingapparatus is formed. Besides, the submount further comprises the circuitlayout electrically connected to the electrode of the light-emittingdevice via an electrical conductive structure such as a metal wire.

SUMMARY OF THE DISCLOSURE

A light-emitting device, comprising: a substrate comprising an uppersurface; an ion implantation region in the substrate; a semiconductorlayer formed on the upper surface; a light-emitting stack formed on thesemiconductor layer; and multiple cavities formed between thesemiconductor layer and the upper surface in accordance with the ionimplantation region.

A method of manufacturing a light-emitting device, comprising the stepsof: providing a substrate; forming a mask block on the substrate andexposing a portion of the substrate; implanting an ion into the portionof the substrate to form an ion implantation region; and growing asemiconductor stack on the substrate such that multiple cavities areformed between the semiconductor stack and the ion implantation region.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1F show a manufacturing method of a light-emitting device inaccordance with a first embodiment of the present application.

FIG. 2 shows a light-emitting device in accordance with a secondembodiment of the present application.

FIGS. 3A to 3F show three groups of scanning electron microscope photosin accordance with three different densities of the scattering cavitiesdisclosed in the embodiments of the present application.

FIGS. 4A to 4D show a manufacturing method of a light-emitting device inaccordance with a third embodiment of the present application.

FIGS. 5A to 5E show a manufacturing method of a light-emitting device inaccordance with a fourth embodiment of the present application.

FIGS. 6A to 6E show a manufacturing method of a light-emitting device inaccordance with a fifth embodiment of the present application.

FIGS. 7A to 7E show a manufacturing method of a light-emitting device inaccordance with a sixth embodiment of the present application.

FIGS. 8A to 8C show a manufacturing method of a light-emitting device inaccordance with a seventh embodiment of the present application.

FIGS. 9A to 9E show a manufacturing method of a light-emitting device inaccordance with an eighth embodiment of the present application.

FIGS. 10A to 10D show a manufacturing method of a light-emitting devicein accordance with a ninth embodiment of the present application.

FIGS. 11A to 11B show a manufacturing method of a light-emitting devicein accordance with a tenth embodiment of the present application.

FIGS. 12A to 12B show a manufacturing method of a light-emitting devicein accordance with an eleventh embodiment of the present application.

FIGS. 13A to 13B show a manufacturing method of a light-emitting devicein accordance with a twelfth embodiment of the present application.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS First Embodiment

Referring to FIGS. 1A to 1E, a manufacturing method of a light-emittingdevice in accordance with a first embodiment of the present applicationis disclosed. As shown in FIG. 1A, a substrate 102 including an uppersurface 102 a is provided, and an ion implantation region 102 b can beformed on the upper surface 102 a. The ion implantation region 102 b canbe formed by implanting ions into the substrate 102, and the ion can beAr ion, Si ion, O ion, N ion, C ion and the combination thereof, and inthe embodiment, the ion can be Ar. The ion implantation region 102 b canhave a thickness h smaller than 1 μm, preferably between 10 nm to 50 nm,and the ion implantation region 102 b can be formed with an ionimplantation dose between 1E15 ions/cm2 and 1E17 ions/cm2. The substrate102 can be a single-layer and single-crystalline substrate includingsapphire, Si or SiC. The ion implantation region 102 b with a dot-likepattern forms amorphization on partial area of the upper surface 102 aof the substrate 102. In the embodiment, the substrate 102 is sapphire,and a nitride based semiconductor can be grown on the upper surface 102a. Before forming the ion implantation region 102 b, a mask (not shown)with a pattern can be formed on the upper surface 102 a, and ionimplantation region 102 b can be formed in accordance with the patternof the mask. As shown in FIG. 1B, the substrate 102 can be disposed inan MOCVD chamber (not shown), then a semiconductor layer 104 is formedon the upper surface 102 a of the substrate 102 by epitaxial growth.Because of the amorphization of the ion implantation regions 102 b, theepitaxial growth rate on a region other than the implantation regions102 b is faster than that on the implantation regions 102 b, andtherefore a plurality of openings 105 is formed. The semiconductor layer104 serves as a buffer layer to reduce the lattice mismatch between thesubstrate 102 and a light-emitting stack, and the material of thesemiconductor layer 104 can be an undoped GaN or un-intentionally dopedGaN. Along the growth of the semiconductor layer 104, thecross-sectional area of each of the openings 105 is gradually smallerfrom bottom to top. A seed layer (not shown) such as AlN can be formedon the upper surface 102 a of the substrate 102 before the semiconductorlayer 104 is formed. As shown in FIG. 1C, epitaxial growth of thesemiconductor layer 104 is paused after the semiconductor layer 104reach a thickness of about 200 nm to 600 nm, then a barrier section 106can be formed on the semiconductor layer 104 by deposition in the MOCVDchamber. The amount of the deposited barrier section 106 is small so thebarrier section 106 covers only partial regions of the semiconductorlayer 104. The barrier section 106 can be formed of non-crystallinematerial such as SiNx, and in accordance with the existence of theopenings 105, the barrier section 106 can surround each of the openingsfrom top view. As shown in FIG. 1D, after forming the barrier section106, the epitaxial growth of the semiconductor layer 104 is resumed. Theepitaxial growth of the semiconductor layer 104 nearby each opening 105includes a growing direction laterally toward the opening 105, andtherefore the opening 105 can be eventually closed by the semiconductorlayer 104. Because of the barrier section 106 embedded in thesemiconductor layer 104, the growing direction of the semiconductorlayer 104 nearby the openings 105 can be temporarily changed so theopenings 105 can be developed to a desired height before forming aclosed end. The process of embedding the barrier section 106 in thesemiconductor layer 104 can be performed for 1 to 100 cycles, and thesemiconductor layer 104 can be grown with a thickness of between 10 nmto 50 nm during each cycle. As shown in FIG. 1E, the openings 105 inFIG. 1D are closed when the semiconductor layer 104 is grown to reach athickness of about 2.5 μm to 3 μm, and a plurality of scatteringcavities 105 a can be formed. As shown in FIG. 1F, a light-emittingstack 114 which includes an n-type semiconductor layer 108, an activelayer 110, and a p-type semiconductor layer 112 in the embodiment can beformed on the semiconductor layer 104. The electrons provided from then-type semiconductor layer 108 and the holes provided from the p-typesemiconductor layer 112 combine in the active layer 110 to emit light Lunder an external electrical driving current, and light L emitted fromthe active layer 110 can be scattered by the scattering cavities 105 aso the light-extraction of the light-emitting device 100 can beenhanced. In the embodiment, the ion implantation region 102 b isamorphous, and the scattering cavities 105 a are directly on the ionimplantation region 102 b. Each of the scattering cavities 105 aincludes a bottom surface 105 b being a region of the upper surface 102a of the substrate 102 and a side surface 105 c connected to the bottomsurface 105 b. The p-type semiconductor layer 112 can have an unevenupper surface 112 a for scattering the light L from the active layer110. The light-emitting stack 114 can include nitride basedsemiconductor, and in the embodiment, the light-emitting stack 114 canbe GaN. The form of each of the cavities 105 a can be cone, pyramid orother forms having a wide bottom and a narrow top.

Second Embodiment

Referring to FIG. 2, a light-emitting device in accordance with a secondembodiment of the present application is disclosed. A light-emittingdevice 200 includes: a substrate 202 including an upper surface 202 a;an ion implantation region 202 b formed on the upper surface 202 a; asemiconductor layer 204 formed on the upper surface 202 a; alight-emitting stack 214 formed on the semiconductor layer 204; and aplurality of scattering cavities 205 formed between the semiconductorlayer 204 and the upper surface 202 a in accordance with the ionimplantation region 202 b and configured to scatter the light L emittedfrom the light-emitting stack 214. The difference between the embodimentand the first embodiment is that the ion implantation region 202 b formsa crystallized region for epitaxial growth and has a mesh-like patternfrom top view, and the scattering cavities 205 are formed on the uppersurface 202 a rather than the ion implantation region 202 b. In theembodiment, the light-emitting stack 214 includes an n-typesemiconductor layer 208 formed on the semiconductor layer 204, an activelayer 210 formed on the n-type semiconductor layer, and a p-typesemiconductor layer 212 formed on the active layer 210. The p-typesemiconductor layer 212 includes an uneven upper surface 212 a being aprimary surface for extracting light L emitted from the active layer210, and the roughness of the uneven upper surface 212 a is forscattering light L emitted from the active layer 210.

Referring to FIGS. 3A to 3F, a couple sets of scanning electronmicroscope photos shows different densities of the scattering cavitiesdisclosed in the embodiments of the present application are shown. FIGS.3A and 3B, FIGS. 3C and 3D, and FIGS. 3E and 3F represent three sets ofdifferent densities of the scattering cavities, respectively. Thescattering cavities are arranged in hexagonal close-packed with apredetermined pitch between two adjacent scattering cavities.

Third Embodiment

Referring to FIGS. 4A to 4D, a method of forming a plurality ofscattering cavities between a substrate 102 and a semiconductor layer104 in accordance with the third embodiment of the present embodiment isdisclosed. As FIG. 4A shows, a metal film 301 is formed on an uppersurface 102 a of the substrate 102 by PVD or CVD, wherein the uppersurface 102 a is planar. The material of the metal film 301 comprisesAu, Ag, Ni, or Al, and the metal film 301 has a thickness h1 between50˜100 nm. Then, as FIG. 4B shows, the metal film 301 can be applied aheat treatment to form multiple metal particles 301 a on the uppersurface 102 a and reveal a portion of the upper surface 102 a, whereinthe heat treatment comprises heating the metal film 301 to 600˜800° C.,maintaining the metal film 301 in a temperature of 600˜800° C. for about30˜60 seconds and cooling the metal film 301 to about 200° C. by usingnitrogen gas. When the metal film 301 is heated, the molecules of themetal film 301 are attracted to each other due to the cohesive force andbecome semi-molten metal, which is able to form the multiple metalparticles 301 a. An interval g1 between any two of the neighboring metalparticles 301 a is smaller than 1 μm, and the particle size d1 of themetal particle 301 a is between 50˜500 nm. The interval g1 between anytwo of the neighboring metal particles 301 a and the particle size d1 ofthe metal particle 301 a can be controlled by the period of maintainingthe metal film 301 in a temperature of 600˜800° C. As the period ofmaintaining the metal film 301 in a temperature of 600˜800° C. isshorter, the interval g1 and the particle size d1 are smaller. As FIG.4C shows, ions 9 are implanted into the substrate 102. The multiplemetal particles 301 a can act as a mask to the ions 9 which areimplanted to the portion of the upper surface 102 a exposed from themultiple metal particles 301 a to form ion implantation regions 102 b.The ion can be Ar ion, Si ion, O ion, N ion, C ion and the combinationthereof. As FIG. 4D shows, the multiple metal particles 301 a areremoved by wet etching, and a semiconductor layer 104 is formed on theupper surface 102 a by epitaxial growth. Because of the amorphization ofthe ion implantation regions 102 b, the epitaxial growth rate on aregion other than the implantation regions 102 b is faster than that onthe implantation regions 102 b, and therefore multiple openings areformed on the implantation regions 102 b. As the semiconductor layer 104is grown to reach a thickness of about 2.5 μm to 3 μm, the multipleopenings are closed to form multiple scattering cavities 105 a betweenthe substrate 102 and the semiconductor layer 104 and on the ionimplantation regions 102 b. The height H of the scattering cavity 105 a,which is smaller than 1 μm, can be controlled by the category, dose andenergy of the ions 9.

Fourth Embodiment

Referring to FIGS. 5A to 5E, a method of forming a plurality ofscattering cavities between a substrate 102 and a semiconductor layer104 in accordance with the fourth embodiment of the present embodimentis disclosed. As FIG. 5A shows, a metal film 301 is formed on the uppersurface 102 a of the substrate 102 by PVD or CVD, wherein the uppersurface 102 a is planar. The material of the metal film 301 comprisesAu, Ag, Ni, or Al, and the metal film 301 has a thickness h1 between50˜100 nm. Then, as FIG. 5B shows, a heat treatment can be applied tothe metal film 301 to form multiple metal particles 301 a on the uppersurface 102 a and reveal a portion of the upper surface 102 a, whereinthe heat treatment comprises heating the metal film 301 to 600˜800° C.,maintaining the metal film 301 in a temperature of 600˜800° C. for about30˜60 seconds and cooling the metal film 301 to about 200° C. by usingnitrogen gas. When the metal film 301 is heated, the molecules of themetal film 301 are attracted to each other due to the cohesive force andbecome semi-molten metal, which is able to form the multiple metalparticles 301 a. An interval g1 between any two of the neighboring metalparticles 301 a is smaller than 1 μm, and the particle size of the metalparticle 301 a is between 50˜500 nm. The interval g1 between any two ofthe neighboring metal particles 301 a and the particle size d1 of themetal particle 301 a can be controlled by the period of maintaining themetal film 301 in the temperature of 600˜800° C. As the period ofmaintaining the metal film 301 in the temperature of 600˜800° C. isshorter, the interval g1 and the particle size d1 are smaller. As FIG.5C shows, a concave region 107 a between the metal particles 30 isformed by etching the portion of the upper surface 102 a exposed fromthe multiple metal particles 301 a, and the portion of the upper surface102 a under the multiple metal particles 301 a forms multiplemicro-protrusions 107 b, wherein the etching process comprises dryetching, such as RIE and ICP, or wet etching. The concave region 107 ahas a depth d2 usually smaller than 30 nm which can be controlled by theetching time. The multiple micro-protrusions 107 b are randomly arrangedover the upper surface 102 a. As FIG. 5D shows, ions 9 is implanted intothe substrate 102. The multiple metal particles 301 a can act as a maskto the ions 9 which can be implanted to the portion of the upper surface102 a exposed from the multiple metal particles 301 a to form ionimplantation regions 102 b in the concave portion 107 a, instead of themultiple micro-protrusions 107 b. The ion can be Ar ion, Si ion, O ion,N ion, C ion and the combination thereof. As FIG. 5E shows, the multiplemetal particles 301 a are removed by wet etching and a semiconductorlayer 104 is formed on the upper surface 102 a by epitaxial growth.Because of the amorphization of the ion implantation regions 102 b, theepitaxial growth rate on a region other than the implantation regions102 b is faster than that on the implantation regions 102 b, andtherefore multiple openings are formed on the implantation regions 102b. As the semiconductor layer 104 is grown to reach a thickness of about2.5 μm to 3 μm, multiple scattering cavities 105 a can be formed betweenthe substrate 102 and the semiconductor layer 104 and on the ionimplantation regions 102 b, and the multiple scattering cavities 105 aand the multiple micro-protrusions 107 b can be formed alternately. Theheight H of the scattering cavity 105 a, which is smaller than 1 μm, canbe controlled by the depth d2 of the concave region 107 a, and thecategory, dose and energy of the ions 9.

Fifth Embodiment

Referring to FIGS. 6A to 6E, a method of forming a plurality ofscattering cavities between a substrate 102 and a semiconductor layer104 in accordance with the fifth embodiment of the present embodiment isdisclosed. As FIG. 6A shows, an oxide layer 302 is formed on an uppersurface 102 a of the substrate 102 by PVD or CVD, wherein the uppersurface 102 a is planar and the thickness of the oxide layer 302 issmaller than 500 nm. The oxide layer 302 comprises SiOx and has athickness h2 smaller than 500 nm, or preferably between 50˜150 nm. Then,a metal film 301 is formed on the oxide layer 302 by PVD or CVD. Thematerial of the metal film 301 comprises Au, Ag, Ni, or Al, and themetal film 301 has a thickness h1 between 50˜100 nm. As FIG. 6B shows, aheat treatment can be applied to the metal film 301 to form multiplemetal particles 301 a on the oxide layer 302 and reveal a portion of theoxide layer 302, wherein the heat treatment comprises heating the metalfilm 301 to 600˜800° C., maintaining the metal film 301 in a temperatureof 600˜800° C. for about 30˜60 seconds and cooling the metal film 301 toabout 200° C. by using nitrogen gas. When the metal film 301 is heated,the molecules of the metal film 301 are attracted to each other due tothe cohesive force and become semi-molten metal, which is able to formthe multiple metal particles 301 a. An interval g1 between any two ofthe neighboring metal particles 301 a is smaller than 1 μm, and theparticle size of the metal particle 301 a is between 50˜500 nm. Theinterval g1 between any two of the neighboring metal particles 301 a andthe particle size d1 of the metal particle 301 a can be controlled bythe period of maintaining the metal film 301 in the temperature of600˜800° C. As the period of maintaining the metal film 301 in thetemperature of 600˜800° C. is shorter, the interval g1 and the particlesize d1 are smaller. As FIG. 6C shows, the portion of the oxide layer302 exposed from the multiple metal particles 301 a is removed by dryetching, such as ICP or RIE, or wet etching to form multiple oxideblocks 302 a between the upper surface 102 a and the multiple metalparticles 301 a. As FIG. 6D shows, the multiple oxide blocks 302 a canact as a mask to an acid etching solution which is used for forming aconcave region 107 a on the portion of the upper surface 102 a exposedtherefrom, and the portion of the upper surface 102 a under the multiplemetal particles 301 a forms multiple micro-protrusions 107 b, whereinthe acid etching solution comprises sulfuric acid, phosphoric acid orthe combination thereof. The concave region 107 a has a depth d2preferably smaller than 30 nm, wherein the depth d2 can be controlled bythe etching time. The multiple micro-protrusions 107 b are randomlyarranged over the upper surface 102 a. And, the multiple metal particles301 a can act as a mask to ions 9 which are implanted to the concaveregion 107 a to form ion implantation regions 102 b therein. The ion canbe Ar ion, Si ion, O ion, N ion, C ion and the combination thereof. AsFIG. 6E shows, the multiple metal particles 301 a and the multiple oxideblocks 302 a are removed by wet etching and a semiconductor layer 104 isformed on the upper surface 102 a by epitaxial growth. Because of theamorphization of the ion implantation regions 102 b, the epitaxialgrowth rate on a region other than the implantation regions 102 b isfaster than that on the implantation regions 102 b, and thereforemultiple openings are formed on the implantation regions 102 b. As thesemiconductor layer 104 is grown to reach a thickness of about 2.5 μm to3 μm, multiple scattering cavities 105 a can be formed between thesubstrate 102 and the semiconductor layer 104 and on the ionimplantation regions 102 b, and the multiple scattering cavities 105 aand the multiple micro-protrusions 107 b can be formed alternately. Theheight H of the scattering cavity 105 a, which is smaller than 1 μm, canbe controlled by the depth d2 of the concave region 107 a, and thecategory, dose and energy of the ions 9.

Sixth Embodiment

Referring to FIGS. 7A to 7E, a method of forming a plurality ofscattering cavities between the substrate 102 and the semiconductorlayer 104 in accordance with the sixth embodiment of the presentembodiment is disclosed. The difference between the sixth embodiment andthe abovementioned third embodiment is that the upper surface 102 a hasa protruded part 120 comprising a plurality of protrusions and a planarpart 121. The multiple protrusions of the protruded part 120 areperiodically arranged over the upper surface 102 a. As FIG. 7A shows, ametal film 301 is formed on an upper surface 102 a. Then, as FIG. 7Bshows, the heat treatment can be applied to the metal film 301 to formmultiple metal particles 301 a on the protruded part 120 and the planarpart 121, wherein the heat treatment comprises heating the metal film301 to 600˜800° C., maintaining the metal film 301 in a temperature of600˜800° C. for about 30˜60 seconds and cooling the metal film 301 toabout 200° C. by using nitrogen gas. When the metal film 301 is heated,the molecules of the metal film 301 are attracted to each other due tothe cohesive force and become semi-molten metal, which is able to formthe multiple metal particles 301 a. An interval between any two of theneighboring metal particles 301 a is smaller than 1 μm, and the particlesize of the metal particle 301 a is between 50˜500 nm. The intervalbetween any two of the neighboring metal particles 301 a and theparticle size of the metal particle 301 a can be controlled by theperiod of maintaining the metal film 301 in a temperature of 600˜800° C.Next, ions 9 are implanted into the substrate 102. The multiple metalparticles 301 a can act as a mask to the ions 9 which are implanted tothe portion of on the protruded part 120 and the planar part 121 exposedfrom the multiple metal particles 301 a to form ion implantation regions102 b. FIG. 7C shows the top view of the multiple metal particles 301 aarranged on a portion of the protruded part 120 and the planar part 121and the ion implantation regions 102 b exposed from the multiple metalparticles 301 a to form ion implantation regions 102 b. FIG.7D shows thescanning electron microscope (SEM) photo of the ion implantation regions102 b and the distribution of the multiple metal particles 301 a on bothof the protruded part 120 and the planar part 121 of the upper surface102 a. The multiple scattering cavities 105 a can be formed on both ofthe protruded part 120 and the planar part 121.

Seventh Embodiment

Referring to FIGS. 8A to 8C, a method of forming a plurality ofscattering cavities between the substrate 102 and the semiconductorlayer 104 in accordance with the seventh embodiment of the presentembodiment is disclosed. The difference between the seventh embodimentand the abovementioned fourth embodiment is that the upper surface 102 ahas a protruded part 120 comprising a plurality of protrusions and aplanar part 121, wherein the multiple protrusions of the protruded part120 are periodically arranged over the upper surface 102 a, and the ionimplantation regions 102 b can be formed on both of the protruded part120 and the planar part 121, and the multiple scattering cavities 105 acan also be formed on both of the protruded part 120 and the planar part121. As FIG. 8A shows, a metal film 301 is formed on the protruded part120 and the planar part 121 by PVD or CVD. The material of the metalfilm 301 comprises Au, Ag, Ni, or Al, and the metal film 301 has athickness between 50˜100 nm. Then, as FIG. 8B shows, a heat treatmentcan be applied to the metal film 301 to form multiple metal particles301 a on the protruded part 120 and the planar part 121 and reveal aportion of the protruded part 120 and the planar part 121, wherein theheat treatment comprises heating the metal film 301 to 600˜800° C.,maintaining the metal film 301 in a temperature of 600˜800° C. for about30˜60 seconds and cooling the metal film 301 to about 200° C. by usingnitrogen gas. When the metal film 301 is heated, the molecules of themetal film 301 are attracted to each other due to the cohesive force andbecome semi-molten metal, which is able to form the multiple metalparticles 301 a. An interval between any two of the neighboring metalparticles 301 a is smaller than 1 μm, and the particle size of the metalparticle 301 a is between 50˜500 nm. The interval between any two of theneighboring metal particles 301 a and the particle size d1 of the metalparticle 301 a can be controlled by the period of maintaining the metalfilm 301 in the temperature of 600˜800° C. As the period of maintainingthe metal film 301 in the temperature of 600˜800° C. is shorter, theinterval and the particle size are smaller. As FIG. 8B shows, a concaveregion 107 a between the metal particles 301 a is formed by etching theportion of the protruded part 120 and the planar part 121 exposed fromthe multiple metal particles 301 a, and the portion of the upper surface102 a under the multiple metal particles 301 a forms multiplemicro-protrusions 107 b, wherein the etching process comprises dryetching, such as RIE and ICP, or wet etching. The concave region 107 ahas a depth usually smaller than 30 nm which can be controlled by theetching time. The multiple micro-protrusions 107 b are randomly arrangedover the upper surface 102 a and a feature size of one of theprotrusions of the protruded part 120 is at least two times of a featuresize of one of the micro-protrusions 107 b. And, ions 9 are implantedinto the substrate 102, and the multiple metal particles 301 a can actas a mask to the ions 9 which can be implanted to the portion ofprotruded part 120 and the planar part 121 exposed from the multiplemetal particles 301 a to form ion implantation regions 102 b in theconcave region 107 a. The ion can be Ar ion, Si ion, O ion, N ion, C ionand the combination thereof. As FIG. 8C shows, the multiple metalparticles 301 a are removed by wet etching and a semiconductor layer 104is formed on the upper surface 102 a by epitaxial growth. Because of theamorphization of the ion implantation regions 102 b, the epitaxialgrowth rate on a region other than the implantation regions 102 b isfaster than that on the implantation regions 102 b, and thereforemultiple openings are formed on the implantation regions 102 b. As thesemiconductor layer 104 is grown to reach a thickness of about 2.5 μm to3 μm, multiple scattering cavities 105 a can be formed between thesubstrate 102 and the semiconductor layer 104 and on the ionimplantation regions 102 b, and the multiple scattering cavities 105 aand the multiple micro-protrusions 107 b can be formed alternately.

Eighth Embodiment

Referring to FIGS. 9A to 9E, a method of forming a plurality ofscattering cavities between the substrate 102 and the semiconductorlayer 104 in accordance with the eighth embodiment of the presentembodiment is disclosed. The difference between the eighth embodimentand the abovementioned fifth embodiment is that the upper surface 102 ahas a protruded part 120 comprising a plurality of protrusions and aplanar part 121, wherein the multiple protrusions of the protruded part120 are periodically arranged over the upper surface 102 a, both of theconcave region 107 a and the ion implantation regions 102 b can beformed on both of the protruded part 120 and the planar part 121, andthe multiple scattering cavities 105 a can also be formed on both of theprotruded part 120 and the planar part 121.

As FIG. 9A shows, an oxide layer 302 is formed on the protruded part 120and the planar part 121 by PVD or CVD. The oxide layer 302 comprisesSiOx and has a thickness smaller than 500 nm, or preferably between50˜150 nm. Then, a metal film 301 is formed on the oxide layer 302 byPVD or CVD. The material of the metal film 301 comprises Au, Ag, Ni, orAl, and the metal film 301 has a thickness between 50˜100 nm. As FIG. 9Bshows, a heat treatment can be applied to the metal film 301 to formmultiple metal particles 301 a on the oxide layer 302 and reveal aportion of the oxide layer 302, wherein the heat treatment comprisesheating the metal film 301 to 600˜800° C., maintaining the metal film301 in a temperature of 600˜800° C. for about 30˜60 seconds and coolingthe metal film 301 to about 200° C. by using nitrogen gas. When themetal film 301 is heated, the molecules of the metal film 301 areattracted to each other due to the cohesive force and become semi-moltenmetal, which is able to form the multiple metal particles 301 a. Aninterval between any two of the neighboring metal particles 301 a issmaller than 1 μm, and the particle size of the metal particle 301 a isbetween 50˜500 nm. The interval between any two of the neighboring metalparticles 301 a and the particle size of the metal particle 301 a can becontrolled by the period of maintaining the metal film 301 in thetemperature of 600˜800° C. As the period of maintaining the metal film301 in the temperature of 600˜800° C. is shorter, the interval and theparticle size are smaller. As FIG. 9C shows, the portion of the oxidelayer 302 exposed from the multiple metal particles 301 a is removed bydry etching, such as ICP or RIE, or wet etching to form multiple oxideblocks 302 a between the upper surface 102 a and the multiple metalparticles 301 a. As FIG. 9D shows, the multiple oxide blocks 302 a canact as a mask to an acid etching solution which is used for forming aconcave region 107 a on the portion of the upper surface 102 a exposedtherefrom, and the portion of the upper surface 102 a under the multipleoxide blocks 302 a forms multiple micro-protrusions 107 b, wherein theacid etching solution comprises sulfuric acid, phosphoric acid or thecombination thereof. The concave region 107 a has a depth preferablysmaller than 30 nm, wherein the depth can be controlled by the etchingtime. The multiple micro-protrusions 107 b are randomly arranged overthe upper surface 102 a and a feature size of one of the protrusions ofthe protruded part 120 is at least two times of a feature size of one ofthe micro-protrusions 107 b. And, the multiple metal particles 301 a canact as a mask to ions 9 which are implanted to the concave region 107 ato form ion implantation regions 102 b therein. The ion can be Ar ion,Si ion, O ion, N ion, C ion and the combination thereof. As FIG. 9Eshows, the multiple metal particles 301 a and the multiple oxide blocks302 a are removed by wet etching and a semiconductor layer 104 is formedon the protruded part 120 and the planar part 121 by epitaxial growth.Because of the amorphization of the ion implantation regions 102 b, theepitaxial growth rate on a region other than the implantation regions102 b is faster than that on the implantation regions 102 b, andtherefore multiple openings are formed on the implantation regions 102b. As the semiconductor layer 104 is grown to reach a thickness of about2.5 μm to 3 μm, multiple scattering cavities 105 a can be formed betweenthe substrate 102 and the semiconductor layer 104 and on the ionimplantation regions 102 b, and the multiple scattering cavities 105 aand the multiple micro-protrusions 107 b can be formed alternately.

Ninth Embodiment

Referring to FIGS. 10A to 10C, a method of forming multiple scatteringcavities between a substrate 102 and a semiconductor layer 104 inaccordance with the ninth embodiment of the present embodiment isdisclosed. As FIG. 10A shows, multiple oxide particles 303 are disposedon an upper surface 102 a of the substrate 102. An interval g2 betweenany two of the neighboring oxide particles 303 is between 200˜300 nm andthe oxide particle 303 has a particle size d3 between 300˜600 nm. Theintervals g2 between the different oxide particles 303 can be the sameor different. FIGS. 10B and 10C show the top view of the arrangements ofthe multiple oxide particles 303. Then, ions 9 are implanted into thesubstrate 102. The multiple oxide particles 303 can act as a mask to theions 9 which are implanted to the portion of the upper surface 102 aexposed from the multiple oxide particles 303 to form ion implantationregions 102 b. The ion can be Ar ion, Si ion, O ion, N ion, C ion andthe combination thereof. As FIG. 10D shows, the multiple oxide particles303 can be removed by wet etching and the semiconductor layer 104 isformed on the upper surface 102 a by epitaxial growth. Because of theamorphization of the ion implantation regions 102 b, the epitaxialgrowth rate on a region other than the implantation regions 102 b isfaster than that on the implantation regions 102 b, and thereforemultiple openings are formed on the implantation regions 102 b. As thesemiconductor layer 104 is grown to reach a thickness of about 2.5 μm to3 μm, multiple scattering cavities 105 a can be formed between thesubstrate 102 and the semiconductor layer 104 and on the ionimplantation regions 102 b. The height H of the scattering cavity 105 a,which is smaller than 1 μm, can be controlled by the category, dose andenergy of the ions 9.

Tenth Embodiment

Referring to FIGS. 11A to 11B, a method of forming multiple scatteringcavities between a substrate 102 and a semiconductor layer 104 inaccordance with the tenth embodiment of the present embodiment isdisclosed. The difference between the tenth embodiment and theabovementioned ninth embodiment is that a concave region 107 a betweenthe oxide particles 303 is formed by etching the portion of the uppersurface 102 a exposed from the multiple oxide particles 303, and theportion of the upper surface 102 a under the multiple oxide particles303 forms multiple micro-protrusions 107 b, wherein the etching processcomprises dry etching, such as RIE and ICP. The concave region 107 a hasa depth d2 preferably smaller than 30 nm, wherein the depth d2 can becontrolled by the etching time. The multiple micro-protrusions 107 b arerandomly arranged over the upper surface 102 a. And, the multiple oxideparticles 303 can act as a mask to ions 9 which are implanted to theconcave region 107 a to form ion implantation regions 102 b therein. Theion can be Ar ion, Si ion, O ion, N ion, C ion and the combinationthereof. As FIG. 11B shows, the multiple oxide particles 303 are removedby wet etching and a semiconductor layer 104 is formed on the uppersurface 102 a by epitaxial growth. Because of the amorphization of theion implantation regions 102 b, the epitaxial growth rate on a regionother than the implantation regions 102 b is faster than that on theimplantation regions 102 b, and therefore multiple openings are formedon the implantation regions 102 b. As the semiconductor layer 104 isgrown to reach a thickness of about 2.5 μm to 3 μm, multiple scatteringcavities 105 a can be formed between the substrate 102 and thesemiconductor layer 104 and on the ion implantation regions 102 b, andthe multiple scattering cavities 105 a and the multiplemicro-protrusions 107 b can be formed alternately. The height H of thescattering cavity 105 a, which is smaller than 1 μm, can be controlledby the depth d2 of the concave region 107 a, and the category, dose andenergy of the ions 9.

Eleventh Embodiment

Referring to FIGS. 12A to 12B, a method of forming multiple scatteringcavities between a substrate 102 and a semiconductor layer 104 inaccordance with the eleventh embodiment of the present embodiment isdisclosed. The difference between the eleventh embodiment and theabovementioned ninth embodiment is that the upper surface 102 a has aprotruded part 120 comprising a plurality of protrusions and a planarpart 121. The multiple protrusions of the protruded part 120 areperiodically arranged over the upper surface 102 a. The multiple oxideparticles 303 can be disposed on both of the protruded part 120 and theplanar part 121. The multiple oxide particles 303 can act as a mask tothe ions 9 which are implanted to the portion of the upper surface 102 aexposed from the multiple oxide particles 303 to form the ionimplantation regions 102 b. As FIG. 10B shows, the ion implantationregions 102 b can be formed on both of the protruded part 120 and theplanar part 121, and the multiple scattering cavities 105 a can also beformed on both of the protruded part 120 and the planar part 121.

Twelfth Embodiment

Referring to FIGS. 13A to 13B, a method of forming multiple scatteringcavities between a substrate 102 and a semiconductor layer 104 inaccordance with the twelfth embodiment of the present embodiment isdisclosed. The difference between the twelfth embodiment and theabovementioned tenth embodiment is that the upper surface 102 a has aprotruded part 120 comprising a plurality of protrusions and a planarpart 121. The multiple protrusions of the protruded part 120 areperiodically arranged over the upper surface 102 a. The multiple oxideparticles 303 can be disposed on both of the protruded part 120 and theplanar part 121, and the concave region 107 a and multiplemicro-protrusions 107 b can be formed on thereof. The multiple oxideparticles 303 can act as a mask to the ions 9 which are implanted to theportion of the upper surface 102 a exposed from the multiple oxideparticles 303 to form the ion implantation regions 102 b in the concaveregion 107 a. As FIG. 13B shows, the multiple scattering cavities 105 acan be formed on both of the protruded part 120 and the planar part 121,and the multiple scattering cavities 105 a and the multiplemicro-protrusions 107 b can be formed alternately.

Although the present application has been explained above, it is not thelimitation of the range, the sequence in practice, the material inpractice, or the method in practice. Any modification or decoration forpresent application is not detached from the spirit and the range ofsuch.

What is claimed is:
 1. A light-emitting device, comprising: a substratecomprising an upper surface; an ion implantation region in thesubstrate; a semiconductor layer formed on the upper surface; alight-emitting stack formed on the semiconductor layer; and multiplecavities formed between the semiconductor layer and the upper surface inaccordance with the ion implantation region.
 2. The light-emittingdevice according to claim 1, wherein the upper surface comprises aconcave portion.
 3. The light-emitting device according to claim 2,wherein the ion implantation region overlaps with the concave portion.4. The light-emitting device according to claim 1, wherein the uppersurface comprises multiple protrusions periodically arranged over theupper surface.
 5. The light-emitting device according to claim 4,wherein one of the multiple protrusions comprises multiplemicro-protrusions randomly arranged over the one protrusion.
 6. Thelight-emitting device according to claim 5, wherein the multiplemicro-protrusions are separated from each other by the concave portion.7. The light-emitting device according to claim 1, wherein the substratecomprises a single-crystalline material and the light-emitting stackcomprises nitride based semiconductor.
 8. The light-emitting deviceaccording to claim 5, wherein the cavities and the micro-protrusions areformed alternately.
 9. The light-emitting device according to claim 5,wherein the shapes of the multiple protrusions are substantially thesame, and the shapes of the multiple micro-protrusions are substantiallydifferent.
 10. The light-emitting device according to claim 1, whereinone of the cavities has a feature size smaller than 1 μm.
 11. A methodof manufacturing a light-emitting device, comprising the steps of:providing a substrate; forming a mask block on the substrate andexposing a portion of the substrate; implanting an ion into the portionof the substrate to form an ion implantation region; and growing asemiconductor stack on the substrate such that multiple cavities areformed between the semiconductor stack and the ion implantation region.12. The method of manufacturing a light-emitting device according toclaim 11, further comprising a step of removing the mask block.
 13. Themethod of manufacturing a light-emitting device according to claim 11,wherein the mask block comprises a material made of metal or oxide. 14.The method of manufacturing a light-emitting device according to claim13, wherein the step of forming the mask block comprises forming a metalfilm on the substrate and applying a heat treatment to the metal film toform multiple metal particles separated from each other.
 15. The methodof manufacturing a light-emitting device according to claim 14, whereina thickness of the metal film is smaller than 100nm.
 16. The method ofmanufacturing a light-emitting device according to claim 14, wherein aparticle size of one of the multiple metal particles is between 50 nmand 500 nm, and a gap between neighboring two of the metal particles issmaller than 1 μm.
 17. The method of manufacturing a light-emittingdevice according to claim 14 further comprising a step of forming anoxide layer on the substrate before forming the metal film on thesubstrate.
 18. The method of manufacturing a light-emitting deviceaccording to claim 17, wherein a thickness of the oxide layer is smallerthan 500 nm.
 19. The method of manufacturing a light-emitting deviceaccording to claim 13, wherein the step of forming the mask blockcomprises disposing multiple oxide particles on the substrate, wherein aparticle size of one of the multiple oxide particles between 300 nm and600 nm, and a gap between neighboring two of the oxide particles issmaller than 1 μm.
 20. The method of manufacturing a light-emittingdevice according to claim 11, further comprising a step of etching theportion of the substrate to form a concave region in the substrate.